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A roadmap for next-generation 2D semiconductor 'gate stack' technology

Seoul National University's College of Engineering announced that a research team led by Professor Chul-Ho Lee from the Department of Electrical and Computer Engineering has outlined a comprehensive ...
EDN

TSMC Uses Applied Gate Stack Tech at 65nm

Applied Materials Inc. said today that Foundry giant Taiwan Semiconductor Manufacturing Co. plans to use Applied's transistor fabrication technology for its 65nm process, extending oxynitride gate ...
Nanowerk

Researchers chart roadmap to unlock next-gen 2D transistor technology

Researchers unveil a roadmap for 2D transistor gate stack design, marking a key step toward ultra-efficient chips that could replace silicon technology. For decades, silicon-based CMOS technology has ...
Semiconductor Engineering

FinFET Isolation: Bulk vs. SOI

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI. It generated immense interest, and created lots of discussion on various LinkedIn groups. In ...
Electronic Design

Keeping Pace with AI: Why Gate-All-Around Transistors are the Answer

Artificial intelligence (AI) has become the workload that defines today’s semiconductor scaling. Whether in hyperscale data centers training foundation models or at the network edge executing ...