Electronics Weekly

LETI integrates III-V lasers on 200mm wafers using CMOS flow

Leti has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V ...
Design-Reuse

Radiation Hardened SRAM Designed by RedCat Devices and Fabricated in TowerJazz's 0.18um Process Flow Withstands 15 Mrad Total Ionization Dose

Developed technology in TowerJazz commercial foundry opens multi-billion markets requiring specific components able to withstand high dose radiation Applications include electronics for communication, ...
EDN

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...
EDN

Performance grows with integration

The manufacturing process flow has been designed to allow all standard CMOS steps to occur at the front end of the process, with the micromachining steps performed after the circuitry is completed.
Electronics Weekly

CMOS will cut cost of integrated photonics, says Leti

Leti says it has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. “This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V ...
Design-Reuse

X-FAB Partners With Akustica to Deliver World's First CMOS MEMS Single-Chip Microphones

X-FAB to Provide Foundry Services for Akustica's Family of CMOS MEMS Silicon Microphone Chips ERFURT, GERMANY and PITTSBURGH, PA -- May 31, 2006 -- Akustica, Inc., a pioneer in acoustic system-on-chip ...
Electronic Design

Simplified High-k/Metal-Gate Process Increases Planar CMOS Speed

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...