UVM testbenches for blocks are adequate until the stage of a subsystem with one or more processors. The new generation of constrained-random test cases based on scenario models can take it from there.

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...

New chip development cycles have decreased to a year, and the time to create a derivative has shrunk to six months. How can chip verification, which takes up 50 to 70 percent of today's development ...

As with death and taxes, when it comes to design some things are just inevitable. For one, as design geometries shrink, design complexity will continue to increase. For another, verification is the ...

Many electronic design automation (EDA) solutions have evolved, which is not a bad thing. Evolution attempts to preserve the tools that are already in place—investments made by designers in languages, ...