Artificial intelligence (AI) has become the workload that defines today’s semiconductor scaling. Whether in hyperscale data centers training foundation models or at the network edge executing ...
Researchers at Peking University have scaled the physical gate length of a ferroelectric transistor down to 1nm and propose a novel “nanogate ultra-low-power ferroelectric transistor” architecture. By ...
Researchers at National Taiwan University have developed a unified model that explains how thickness, defects, interface ...
Tech Xplore on MSN
Key transistor for next-generation 3D stacked semiconductors operates without current leakage
A research team led by Professor Jae Eun Jang and Dr. Goeun Pyo from the Department of Electrical Engineering and Computer Science at DGIST has developed "dual-modulated vertically stacked transistors ...
Morning Overview on MSN
China claims sub-1 nm transistor that cuts power use for AI chips
A team of Chinese researchers has built a ferroelectric transistor with a gate length of just 1 nanometer that runs on 0.6 volts, a fraction of the voltage required by today’s commercial chip ...
A new technical paper titled “Lateral Semiconductor–Free-Space Gate Transistors” was published by researchers at KAUST and the Indian Institute of Technology.
What does 5nm even mean? It’s not about tiny ants, but it is a big deal for how your gadgets work. The size, measured in ...
This whitepaper gives a compact overview of the recommended gate drive concepts for both GIT (gate injection transistor) and SGT (Schottky gate transistor) product families. A versatile standard drive ...
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