Semiconductor Engineering

Front-End Technologies Are The New Back-End Tools: Using Picosecond Ultrasonics Technology For AI Packages, Part 1

If you are a part of the semiconductor industry or simply someone interested in the field, you have likely heard what has become a common refrain: the back-end of the process is becoming more like the ...
Morningstar

Taiyo Holdings Launches Next-generation Semiconductor-packaging Material "FPIM (TM) Series," Its First Successful Formation of 3-layer RDL with CD 1.6 Micrometers on 12-inch Wafer

- Paper Presented at 14th IEEE CPMT Symposium Japan (ICSJ 2025) - TOKYO, Nov. 13, 2025 /PRNewswire/ -- On November 13, 2025, Taiyo Holdings Co., Ltd. (Securities Code: 4626; hereinafter referred to as ...
Semiconductor Engineering

A Hybrid PLP Technology Based On A 650mm x 650mm Platform

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, ...
EDN

Basics of chip/package codesign in a large flipchip application (Part 2 of 2)

A high-speed parallel bus, such as a double data rate (DDR) memory interface, requires a different approach because the speeds are lower but the number of signals involved is much larger. The design ...